1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor memory device. More particularly, the present invention relates to a method for manufacturing a semiconductor memory device having a floating gate, a control gate and asymmetrical source/drain regions.
2. Related Arts
A typical method for manufacturing a flash memory which is a conventional asymmetrical non-volatile semiconductor memory device will be hereinafter explained with reference to FIGS. 14 and 8(a) to 13(c). FIG. 14 is a top view of a flash memory which is an asymmetrical non-volatile semiconductor device. FIGS. 8(a) to 10(c) each represent a view showing a cross section along the line X--X for explaining a method for manufacturing the conventional asymmetrical semiconductor memory device of FIG. 14. FIGS. 11(a) to 13(c) each represent a view showing a cross section along the line Y--Y for explaining the method for manufacturing the conventional asymmetrical semiconductor memory device of FIG. 14.
First, a gate oxide film 22 is formed to a thickness of about 100 .ANG. on a surface of a p-type silicon substrate 21, and then a polysilicon layer 23 for a floating gate is formed to a thickness of 2000 .ANG.. Further, an implantation of phosphorus ions (.sup.31 P.sup.+) is carried out into the polysilicon layer 23 with an implantation energy of 40 keV in a dose of 2.0.times.10.sup.15 cm.sup.-2. Subsequently, a thin nitride film 24 is deposited to a thickness of 600 .ANG. on the polysilicon layer 23 (FIGS. 8(a) and 11(a)).
Then, a resist pattern 25 is formed on the thin nitride film 24 so as to cover the entire surface of an active region in the silicon substrate 21. In use of the resist pattern 25 as a mask, the nitride film 24, the polysilicon layer 23 and the gate oxide film 22 are successively etched (FIGS. 8(b) and 11(b)).
Subsequently, the resist pattern 25 is removed and an implantation of arsenic ions (.sup.75 As.sup.+) is carried out into the entire surface of the silicon substrate 21 with an implantation energy of 40 keV in a dose of 5.0.times.10.sup.13 cm.sup.-2 to form an n-type impurity region 26 of low concentration in the silicon substrate 21 (FIGS. 8(c) and 11(c)).
Then, a resist pattern 27 is formed so as to cover only a source-side region 26a of the n-type impurity region 26 of low concentration. In use of the resist pattern 27 and the nitride film 24 as a mask, an implantation of arsenic ions (.sup.75 As.sup.+) is carried out into the entire surface of the silicon substrate 21 with an implantation energy of 40 keV in a dose of 3.0.times.10.sup.15 cm.sup.-2 to form an n-type impurity region 28 of high concentration in the silicon substrate 21 (FIGS. 8(d) and 11(d)).
Subsequently, the resist pattern 27 is removed and an HTO film 29 of SiO.sub.2 (insulating film) is laminated to a thickness of 3000 .ANG. on the entire surface of the silicon substrate 21 by means of CVD method (FIGS. 9(a) and 12(a)). Subsequently, by etching back the HTO film 29, a side wall spacer 30 is formed only on the side wall of the nitride film 24 and the floating gate 23. Further, in use of this side wall spacer 30 and the nitride film 24 as a mask, an implantation of arsenic ions (.sup.75 As.sup.+) is carried out into the entire surface of the silicon substrate 21 with an implantation energy of 40 keV in a dose of 2.0.times.10.sup.15 cm.sup.-2 to form an n-type impurity region 31 of low concentration and an n-type impurity region 32 of high concentration in a self-aligned manner in the silicon substrate 21 (FIGS. 9(b) and 12(b)).
Next, an interlayer insulating film 33 (a thermal oxide film or an HTO film) is deposited on the entire surface of the silicon substrate 21 (FIGS. 9(c) and 12(c)) followed by flattening the surface of the silicon substrate 21 by CMP method and then, the nitride film 24 is removed by heated phosphoric acid (FIGS. 10(a) and 13(a)).
Subsequently, in order to increase a coupling ratio with the gate, a polysilicon layer 34 is deposited to a thickness of 1000 .ANG. on the entire surface of the silicon substrate 21. Further, an ion implantation of phosphorus ions (.sup.31 P.sup.+) is carried out into the entire polysilicon layer 34 with an implantation energy of 60 keV in a dose of 6.0.times.10.sup.14 cm.sup.-2. Next, with a resist pattern (not shown) used as a mask, the polysilicon layer 34 is patterned (FIGS. 10(b) and 13(b)) and then, the resist pattern is removed. Afterwards, an ONO film [HTO film 150 .ANG./SiN film 250 .ANG./HTO film 100 .ANG.] is formed over the entire surface of the silicon substrate 21 and then, a polysilicon layer 36 for a control gate is deposited to a thickness of 1000 .ANG. thereon. Afterwards, an implantation of phosphorus ions (.sup.31 P.sup.+) is carried out into the polysilicon layer 36 with an implantation energy of 60 keV in a dose of 3.0.times.10.sup.15 cm.sup.-2.
Further, a tungsten silicide layer 37 is deposited to a thickness of 1000 .ANG. over the entire surface of the substrate 21 and then, with a resist mask (not shown) used as a mask, the tungsten silicide layer 37, the polysilicon layer 36, the ONO film 35, the polysilicon layers 34 and 23 and the gate oxide film 22 are successively etched (FIGS. 10(c) and 13(c)). By this etching, the polysilicon layers 34 and 36 and the tungsten silicide layer 37 are formed into a first floating gate, a second floating gate and a control gate, respectively.
Afterwards, an NSG film of a thickness of 1000 .ANG. and a BPSG film of a thickness of 5000 .ANG. are deposited by CVD method as an insulating film, followed by performing a melt processing at 900.degree. C. for 10 minutes. Then, a contact hole is formed by photolithography process. Subsequently, an Al--Si--Cu film is deposited to a thickness of 5000 .ANG. by a sputtering method. Next, a metal wiring is formed by photolithography process to complete a flash memory.
However, according to the above-mentioned conventional manufacturing method, it is difficult to control the width of the side wall spacer of the HTO film within a precision range of .+-.0.05 .mu.m because the ion implantation is conducted after forming the side wall spacer of the HTO film. If the width of the side wall spacer is too narrow, a breakdown voltage drops because of a punch-through. On the contrary, if the width of the side wall spacer is too wide, a read-out current decreases and electrical characteristics of a memory cell will not be stable. Moreover, the method for manufacturing the asymmetrical cell is complicated and requires a lot of steps.